View CDB4220_374169.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CDB4220/1/2/3/4 Evaluation Board for CS4220/1/2/3/4
Features
l Demonstrates
General Description
The CDB4220 evaluation board is an excellent means for quickly evaluating the CS4220/1/2/3/4 family of stereo audio CODECS. Evaluation requires an analog signal source and analyzer, digital signal source and analyzer, PC compatible computer for device control and a power supply. System timing can be provided by the CS8412 digital audio receiver, DSP Port or an on-board oscillator. Stereo analog input (XLR) and stereo analog output (coax) is provided. Digital I/O is provided through either the S/PDIF or DSP port. An SPI/I2C serial control port allows the CS4221/2/4 to be configured and controlled using the supplied Windows 95(R) software.
recommended layout and grounding arrangements l CS8412 receives AES/EBU, S/PDIF and EIAJ-340 compatible data l CS8402A transmits AES/EBU, S/PDIF and EIAJ-340 compatible data l Stereo Analog I/O l DSP port for external serial audio I/O l Windows 95(R) software interface to control CS4221/2/4 l Digital and Analog patch areas
ORDERING INFORMATION: CDB4220, CDB4221, CDB4222, CDB4223, CDB4224
Control Port CS4221/22/24 Analog Input (XLR) Analog Input Buffer
CS8402A
S/PDIF Outputs
CS422x
Analog Output (Coax)
Analog Output Buffer
CS8412
S/PDIF Inputs
DSP Port for Clocks & Data
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
APR `00 DS284DB1 1
CDB4220/1/2/3/4
TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. 7. 8. 9. CDB4220 SYSTEM OVERVIEW .............................................................................................. 3 CS4220/1/2/3/4 CODEC ........................................................................................................... 3 CS8412 DIGITAL AUDIO RECEIVER ...................................................................................... 3 CS8402A DIGITAL AUDIO TRANSMITTER ............................................................................ 3 ANALOG INPUT BUFFER ....................................................................................................... 3 ANALOG OUTPUT BUFFER ................................................................................................... 3 DSP PORT ................................................................................................................................ 3 POWER SUPPLY CIRCUITRY ................................................................................................. 3 CDB4221/2/4 CONTROL PORT SOFTWARE ......................................................................... 4
LIST OF FIGURES
Figure 1. Analog In .......................................................................................................................... 7 Figure 2. Analog Out ....................................................................................................................... 8 Figure 3. I/O for Clocks and Data.................................................................................................... 9 Figure 4. CS422x .......................................................................................................................... 10 Figure 5. Control Port Interface ..................................................................................................... 11 Figure 6. Power Supply ................................................................................................................. 12 Figure 7. CS8412 Digital Audio Receiver...................................................................................... 13 Figure 8. CS8402A Digital Audio Transmitter ............................................................................... 14 Figure 9. Top ................................................................................................................................. 15 Figure 10. Top Silkscreen ............................................................................................................. 16 Figure 11. Bottom Silkscreen ........................................................................................................ 17
LIST OF TABLES
Table 1. CDB4220-4 Jumper Selectable Options ........................................................................... 5 Table 2. CDB4220-4 Default Jumper Settings ................................................................................ 6 Table 3. System Connections ......................................................................................................... 6
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS284DB1
CDB4220/1/2/3/4
1. CDB4220 SYSTEM OVERVIEW
The CDB4220 evaluation board is an excellent means of quickly evaluating the CS4220/1/2/3/4 family of stereo audio codecs. Input and output analog interfaces are provided, and a CS8412 digital audio interface receiver and CS8402A digital audio interface transmitter provide an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board allows you to supply external clock and data signals through the 20-pin DSP port. The CDB4220 schematic is partitioned into eleven schematics as shown in Figures 1 though 11. divides the MCLK by 2 to generate the proper clock signal.
5. ANALOG INPUT BUFFER
The analog inputs of the CDB4220/1/2/3/4 use dual op-amps to implement the AC coupled input buffer. This buffer also performs DC level shifting; a resistive divider supplies an approximate 2.3V bias voltage to the op-amps to set the input bias to the converter inputs. The inputs are digitally filtered after conversion to eliminate any offset. A nominal 5.66 Vpp drive to the buffer will apply a 2V rms differential input to the CS4220/1/2/3/4 resulting in a full-scale output.
2. CS4220/1/2/3/4 CODEC
A complete description of each member of the CS4220/1/2/3/4 family is included in each respective product datasheet.
6. ANALOG OUTPUT BUFFER
Each DAC output drives an op-amp that is configured as a differential to single-ended converter. This circuit also performs two-pole Butterworth filtering and is AC coupled to the output jack. Note that the signal paths through the evaluation board are non-inverting.
3. CS8412 DIGITAL AUDIO RECEIVER
Performance of the DAC can be quickly tested by connecting a S/PDIF audio source to the CS8412. The S/PDIF signal may be input through either the optical or coax connector, see Figure 7. Please note that the two input connectors must not be driven simultaneously. The interface for the CS8412 includes a serial bit clock, serial data, left-right clock (FSYNC) and a 256 Fs master clock. The recovered MCLK, SCLK and LRCK provide the necessary clocks for the CS4220/1/2/3/4.
7. DSP PORT
The DSP HEADER (J5) port provides an interface to the serial audio clocks and data of the CS4220/1/2/3/4 and may be used to interface to external digital signal processors for ease in evaluating complete digital audio system solutions. Please note that when the DSP HEADER port is enabled, care should be exercised in using these signals because these lines require the proper buffers to enabled. By setting the DSP mode byte through the control port (CS4221/2/4) or setting the appropriate jumpers (CS4220/3), the data format can be modified to accommodate different DSP processors.
4. CS8402A DIGITAL AUDIO TRANSMITTER
Performance of the ADC can be quickly tested by connecting an analog generator to the left and right inputs and connecting the S/PDIF optical or coaxial output to audio test equipment. The evaluation board relies on the CS8412 or external clocking signals input through the DSP port for all clocking. The recovered clock from the CS8412 receiver has a frequency of 256 Fs. The CS8402A requires a master clock frequency of 128 Fs, and the 74HC74
DS284DB1
8. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board through four binding posts (-12V, +12V, AGND, +5VA) as shown in Figure 6. The +5VA input provides the +5 Volt power to the CS4220/1/2/3/4. Digital power is derived from the analog supply with a resistor and
3
CDB4220/1/2/3/4
additional decoupling capacitors. The 12 V binding posts carry power to the analog input and output buffers. All power supply connections are bypassed with transient suppression diodes and bulk filtering capacitors.
9. CDB4221/2/4 CONTROL PORT SOFTWARE
The CDB4220 is shipped with Windows based software for interfacing with the CS4221/2/4 control port through the DB25 connector, J18. The software can be used to communicate with the CS4221/2/4 in either SPI or I2C mode. Please note that the control port registers are write-only when SPI mode is used. Run SETUP.EXE from the distribution diskette to install the software. Further documentation for the software is available on the distribution diskette in the plain text format file, README.TXT.
4
DS284DB1
CDB4220/1/2/3/4
JUMPER J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J19 J24 J25 J26 J27 J29 J31
PURPOSE Select DSP port as slave Select DSP port as master Enable DSP port, enabling serial data I/O Selects CS422x MCLK source Selects Loopback or Normal routing of data Selects which codec is on the evaluation board DEM0 DIF0(SDA/CDIN) DIF1 CS422x Master/Slave Select SMUTE (CS4222 only) DEM1 Selects which codec is on the evaluation board CS8412 Master/Slave Select RCV PWR CS8412 SDATA Routing CS8412 SCK Routing CS8412 FSYNC Routing CS422x SDOUT Routing
POSITION DISABLE DSP SLAVE
FUNCTION SELECTED Configures DSP Port for slave mode operation*
DISABLE Configures DSP Port for master mode operation* DSP MASTER DISABLE Enables DSP Port operation* DSP ENABLE Disables DSP Port operation* 8412 DSP 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4220/3 4221/2/4 S M OPEN CONNECT OPEN CONNECT OPEN CONNECT OPEN CONNECT OPEN CONNECT CS422x MCLK supplied from CS8412 CS422x MCLK supplied from DSP Port Loopback - Routes SDOUT from A/D to SDIN of D/A Normal Operation CS4220/1/3/4 CS4222 See CS422x datasheet for details See CS422x datasheet for details See CS422x datasheet for details CS422x is configured for slave mode operation CS422x is configured for master mode operation Disables Soft Mute function of CS4222 Enables Soft Mute function of CS4222 See CS422x datasheet for details CS4220/3 CS4221/2/4 CS8412 is configured for slave mode operation CS8412 is configured for master mode operation Disables +5V power to CS8412 Supplies +5V power to CS8412 Routes SDATA to SDIN of CS422x Routes SCK to SCLK of CS422x Routes FSYNC to LRCK of CS422x Routes SDOUT to SDATA of CS8402A
Table 1. CDB4220-4 Jumper Selectable Options
* DSP Port jumper labels on evaluation board are backwards. Please see schematic for clarification.
DS284DB1
5
CDB4220/1/2/3/4
J6 J7 J8 J9 J10 J11
J12 J13 J14 J15 J16 SMUTE (CS4222 only) J17 DEM1 J19 Selects which codec is on the evaluation board J24 CS8412 Master/Slave Select J25 RCV PWR J26 CS8412 SDATA Routing J27 CS8412 SCK Routing J29 CS8412 FSYNC Routing J31 CS422x SDOUT Routing
PURPOSE Select DSP port as slave* Select DSP port as master* Enable DSP port, enabling serial data I/O* Selects CS422x MCLK source Selects Loopback/Normal routing of data Selects which codec is on the evaluation board DEM0 DIF0(SDA/CDIN) DIF1 CS422x Master/Slave Select
CS4220 SLAVE MASTER ENABLE 8412 1 1 1 0 0 1 OPEN 1 1 M CONNECT OPEN CONNECT CONNECT CONNECT
CS4221 SLAVE MASTER ENABLE 8412 1 1 OPEN 1 OPEN 1 OPEN OPEN 0 M CONNECT OPEN CONNECT CONNECT CONNECT
CS4222 SLAVE MASTER ENABLE 8412 1 0 1 1 OPEN 1 1 1 0 M CONNECT OPEN CONNECT CONNECT CONNECT
CS4223 SLAVE MASTER ENABLE 8412 1 1 1 0 0 1 OPEN 1 1 M CONNECT OPEN CONNECT CONNECT CONNECT
CS4224 SLAVE MASTER ENABLE 8412 1 1 OPEN 1 OPEN 1 OPEN OPEN 0 M CONNECT OPEN CONNECT CONNECT CONNECT
Table 2. CDB4220-4 Default Jumper Settings
* DSP Port jumper labels on evaluation board are backwards. Please see schematic for clarification.
CONNECTOR +5VA AGND +12V -12V LEFT RIGHT ANALOG OUT LEFT ANALOG OUT RIGHT XMITTER XMITTER OPT2 RCVR OPT1 RCVR J18 DSP HEADER
INPUT/OUTPUT Input Input Input Input Input Input Output Output Output Output Input Input Input/Output Input/Output +5 Volt Power
SIGNAL PRESENT Analog Ground connection from power supply +12 Volt Power for op-amps -12 Volt Power for op-amps Left channel analog input through XLR connector Right channel analog input through XLR connector Left channel analog output through coaxial connector Right channel analog output through coaxial connector Digital audio interface output through coaxial connector Digital audio interface output through optical connector Digital audio interface input through coaxial connector Digital audio interface input through optical connector I/O for I2C or SPI control port signals through DB25 connector I/O for external serial audio data and clock signals
Table 3. System Connections 6 DS284DB1
R1 1 C2 +
7.87K 3 2
+ 4
8
22
1
C7 .1uF 1 2 R6 8 7.87K +12V 6 R9 7.87K 5 1 OPA2134 U1B 7 C11 .1uF -12V 4
C9 C8 10uF 50V 100pF
C10 100pF
10uF 50V A5V + R10 R11 C12 8.45K 2 10K 1
-12V +12V R12 1 C14 + 2 10uF 50V C15 100pF 3 TP2 1 OPA2134 1 2 R16 8 7.87K +12V 6 R20 7.87K 5 1 OPA2134 U2B 7 C23 .1uF C22 1 U3A -12V R18 C16 100pF R14 7.87K 8 -12V 7.87K 3 8 C13 .1uF
+ 4
4
1 U2A OPA2134 C17 +12V .1uF R13 R15 10K 150
RIGHT
J2 22
+ 4
C20 C19 10uF 50V 100pF
C21 100pF
1M
-12V
4
Figure 1. Analog In 7
-
3
TP1
OPA2134
U3B 7
8
+
-
+
-
+
+
+
DS284DB1
LEFT
J1 10uF 50V C4 100pF C5 100pF R3 7.87K
+12V
C1 .1uF
1 C3 U1A OPA2134 R4 +12V 1M 10pF R2 R5 10K 150
AINL+
-12V
6 C6 5 2200pF R7 10K R8 150 AINL-
AINR+
3 C18 2 2200pF
CDB4220/1/2/3/4
R17 10K R19 150 AINR-
10pF
AOUTL+
1
+
8
2 -12V C28 AOUTL1 + 2 8.25K 10uF 50V 1800pF C30 1.82K
U4A 4 OPA2134
R24
R25
C29
390pF +12V
R26 + 8.25K
1
AOUTR+
1
+
4
6
8
U4B OPA2134
+12V C35 AOUTR1 + 2 8.25K 10uF 50V 1800pF C37 1.82K R32 8.25K
1
8
C24 2 8.25K 10uF 50V 1800pF R23 8.25K 390pF +12V TP3 + 1 J3 PHONO-JACK C25 1.82K C26 C27 .1uF R21 R22 3
LEFT
C69 1uF 50V
+ C31 2 8.25K 10uF 50V 1800pF C32 1.82K R29 8.25K C33 390pF TP4 + 7 J4 PHONO-JACK -12V C34 .1uF R27 R28 -12V
C70 1uF 50V
5
RIGHT
CDB4220/1/2/3/4
R30
R31
C36
390pF
Figure 2. Analog Out
DS284DB1
10
DSP Header
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
MCLK_DSP
1
J6 HDR3X1 9
10
DSP SLAVE
13
4
MCLK_8412
XTI
XTO
TP5
1 J9 1 2 3 HDR3X1 R33 NOT STUFFED R34 D5V NOT STUFFED
DISABLE DSP ENABLE
1 2 3
HDR3X1
5
4
1
1
TP6
C39 39pF
CRYSTAL
C40 39pF
12
13
DS284DB1
D5V 1 C38 .1uF 7 GND Out U5 XCO 8 9 14 NC VCC 14 A5V U7C 7 74VHC125 8 74VHC125 U6A 74VHC125 HDR10X2 J5 3 2 D5V 5 1 2 3 U6B 6 HDR3X1 D5V J7 1 2 3 SCLK_422x C71 .1uF C72 .1uF
12.288 MHz
DISABLE
DISABLE DSP MASTER
8 U6C
12 74VHC125
U6D 11 74VHC125
LRCK_422x
74VHC125 U7A 3 D5V 2 SDOUT_422x
J8
6 U7B
CDB4220/1/2/3/4
SDIN_422x
MCLK_DSP R35 49.9 Y1
74VHC125
11
U7D 74VHC125
Figure 3. I/O for Clocks and Data 9
/RST_422x
SCL/CCLK
SDA/CDIN
AOUTR+
AOUTL+
AOUTR-
AOUTL-
AD0/CS
AINL+
AINR+
XTI
R39 49.9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC NC U8 CS422x XTO /RST XTI AOUTLLRCK AOUTL+ AOUTR+ SCLK AOUTRVD DGND AGND VA SDOUT SDIN AINL+ DIF1 (SCL/CCLK) AINLDIF0 (SDA/CDIN) DEM1 (I2C/SPI) DEM0 (AD0/CS) ANIR+ 5V/3.3V AINRNC NC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1
AINR-
LRCK_422x XTO
AINL-
I2C/SPI
4220/1/3/4
J11 HDR3X1
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
J12 HDR3X1
J13 HDR3X1
J14 HDR3X1
J15 HDR3X1
J16 HDR3X1
J17 HDR3X1
Figure 4. CS422x
1 2 3
10
J10 SDIN_422x 1 2 3 HDR3X1 R38 49.9 R36 49.9 SDOUT_422x R37 49.9 SCLK_422x
LOOP BACK
A5V
R40 2.2 Ohms
C41
C42
1uF 50V .1uF +
C43 .1uF
C44 1uF 50V
+
TP7 TP8 TP9 TP10TP11TP12TP13TP14TP15TP16TP17 1 A5V 1 1 1 1 1 1 1 1 1 1
TP18TP19TP20TP21TP22TP23TP24TP25TP26TP27TP28 1 1 1 1 1 1 1 1 1 1
4222
R41 47K
R42 47K
R43 2K
R44 47K
R45 47K
R46 47K
R47 47K
DEM0
A5V A5V
DIF0 SDA/CDIN
A5V
DIF1
A5V
S/M
A5V
/SMUTE
A5V
DEM1
CDB4220/1/2/3/4
DS284DB1
2 3 4 5 6 7 8
DB25M_RA J18
D5V .1uF _WRITE_EN _/RST_422x _SCL/CCLK _WRITE_SDA _AD0/CS _I2C/SPI 20 2 3 4 5 6 7 8 9 11 1 10 D5V D1 D2 D3 D4 D5 D6 D7 D8 CLK OC GND U10 74HCT574 1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 19 18 17 16 15 14 13 12 2 D1 BAT85 2
1
1 2 3
4220/3
J19 HDR3X1 4
4221/2/4
S1 1 5 B3W_1100 3
D2 BAT85
2
1
RESET
12
13
1uF 50V
10
DS284DB1
D5V RN1 D5V 1 1K R48 47K R49 R50 R51 R52 R53 R54 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K C45 U9A 3 74HCT125 SCL/CCLK AD0/CS I2C/SPI SDA/CDIN 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 74HCT125 _READ_SDA _LATCH U9B 6 D5V D5V D5V R55 74HCT125 4.99K 511K 9 + R57 511 C46 U9C 8 /RST_422x R56
Schottky Diodes
5
CDB4220/1/2/3/4
11 U9D 74HCT125
C47 D5V .1uF
Figure 5. Control Port Interface 11
1
2
C48 D3 + 100uF 6.3V C50 .1uF TP31 P6KE6.8A
2.2 Ohms +
C49 C51 .1uF 100uF 6.3V 1 TP32
RED J21 1 1
1
BLACK J22 1 2 C52 D4 BLUE P6KE13A 100uF 16V 1 C54 + D5 J23 1 1 1 P6KE13A .1uF 100uF 16V -12V TP35 C55 1 + C53 .1uF TP34 1 TP33 +12V
2
1
12
J20 1 TP29 A5V R58 TP30 D5V
DGND
CDB4220/1/2/3/4
GREEN
DS284DB1
Figure 6. Power Supply
DS284DB1
D6 1 LED D5V R60 J25 HDR2X1 47K 2 R59 1.10K
S/M
1 2 3 J24 HDR3X1
Receiver Power
C56 1uF 50V
+
C57 U11 .1uF TP36 TP37 TP39 TP40 TP42 TP43 1 2 3 4 5 6 7 8 9 10 11 12 13 1 14 TP46 1 1 1 1 1 1 C CD/F1 CC/F0 CB/E2 CA/E1 /C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U VERF CE/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL 28 27 1 26 25 1 24 23 22 21 20 19 18 17 16 15 1 TP47 R65 47K CS8412
R61 10
CONNECT
TP38 TP41 C59 + .1uF 1uF 50V 1 TP45 R64 1K C62 .047uF R62 49.9 1 2 3 J32 HDR3X1 MCLK_8412 C60 1 2 3 J26 HDR3X1 SDIN_422x
OPT1 6 NC OUT GND1 VCC GND2 5 NC TORX173 1 2 3 4 C61 .1uF R63 L1 47uH D5V C58 .01uF
OPEN
TP44
1
47K
PHONO-JACK J28
C63
.01uF
1 2 3
J27
CDB4220/1/2/3/4
HDR3X1 SCLK_422x J29 HDR3X1 LRCK_422x
R66 75 1 2 3
Figure 7. CS8412 Digital Audio Receiver 13
PR
D CLK
Q
D CLK
PR
2 MCLK_8412 SDOUT_422x LRCK_422x SCLK_422x 3
4
U12A 5 12 11
10
CL
Q
6 74HC74
CL
D5V PHONO-JACK T1 C64 2 R67 374 1 D5V .1uF R68 4 90.9 6 TRANSFORMER C65 5 J30 8
SDOUT to 8402
J31 HDR2X1 D5V
.1uF
13
1
14
D5V U12B Q 9 Q 8 74HC74 OPT2 D5V U13 1 2 3 4 5 6 7 8 9 10 11 12 CS8402 R69 /C7/C3 TRNPT/FC1 /PRO M2 /C1/FC0 M1 /C6/C2 M0 MCK TXP SCK VD+ FSYNC GND SDATA TXN V /RST C/SBF CBL/SBC U EM0/C9 /C9/C15 EM1/C8 24 23 22 21 20 19 18 17 16 15 14 13 6.19K 2 3 4 D5V C67 1 TP48 .1uF + C66 1uF 50V C68 .1uF NC TOTX173 1 NC GND CLR VCC 6
CDB4220/1/2/3/4
INPUT 5
/RST_422x
DS284DB1
Figure 8. CS8402A Digital Audio Transmitter
CDB4220/1/2/3/4
DS284DB1
Figure 9. Top 15
16
CDB4220/1/2/3/4
DS284DB1
Figure 10. Top Silkscreen
DS284DB1
CDB4220/1/2/3/4
Figure 11. Bottom Silkscreen 17

▲Up To Search▲

Price & Availability of CDB4220

	To Download CDB4220 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .